1. Field of the Invention
The present invention relates to a wafer level packaging procedure for making wafer level packages. The invention relates also to a semiconductor package made by means of the application of the wafer level packaging procedure.
2. Background of the Invention
A conventional wafer level packaging technique applies electric conducting pastes to the surface of every die zone of the wafer to be packaged, to form conductors that extend from every bonding pad to a predetermined location. Taiwan Patent No. 434848, issued to the present inventor, teaches a similar design. During formation of conductors with electric conducting pastes, the electric conducting pastes are applied to the wafer with a steel plate by printing. The steel plate has a plurality of through holes corresponding to the bonding pads at the wafer. During printing, the steel plate is put on the surface of the wafer, and then the electric conducting pastes are applied to the through holes of the steel plate by means of a printing head. When hardened, the printed electric conducting pastes form the desired conductors subject to the predetermined shapes.
Following improvement of semiconductor manufacturing process, the count of die zones on a wafer is relatively increased, and the area of the die zone on the wafer is relatively reduced. In consequence, the number of bonding pads at the wafer is relatively increased, i.e., the pitch between two adjacent bonding pads is greatly reduced. However, the hole width of the through holes on a steel plate for the aforesaid electric conducting pastes printing process cannot be smaller than 25 mm due to technical limitations. According to conventional techniques, a steel plate cannot be used to print electric conducting pastes on a wafer to make conductors thinner than 25 mm.